Planar coaxial circuitry

ABSTRACT

A STRUCTURE FOR SUPPORTING AND INTERCONNECTING ELECTRICAL CIRCUIT COMPONENTS. THE STRUCTURE IS COMPRISED OF A STACK OF ELECTRICALLY CONDUCTIVE PLATES. INTERCONNECTIONS, EFFECTIVELY CONSTITUTING COAXIAL TRANSMISSION LINES, ARE FORMED USING THE CONDUCTIVE PLATES AS GROUND PLANES. ALIGNED RECESSES ARE FORMED IN OPPOSED SURFACES OF THE   PLATES. DIELECTRIC MATERIAL IS DISPOSED IN THE RECESSES WITH A CONDUCTIVE PATH BEING FORMED BETWEEN THE DIELECTRIC MATERIAL FILLED RECESSES. ADJACENT PLATES ARE BONDED TOGETHER BY AN ELECTRICALLY CONDUCTIVE BONDING MATERIAL.

March 23, 1971 5, 5 ETAL Re. 27,089

PLANAR COAXIAL CIRCUITRY Original Filed Feb. 4.. 1965 3 Sheets-Sheet 1 Mlb 5 ry xw mm \c nvvavroes BRIAN E. SEAR 5:, 2 I AM YM 0ND A. STEPHENSROBE/27C. W/Ll/AMS v Mmh23, 1971 SEAR ETAL I Re. 27,089

PLANAR COAXIAL CIRCUI'IRY Original Filed Feb. 4. 1965 5 Sheets-Sheet 2 11L 43 l MANuFAcTumNe PROCESS a AN ALUMINUM PLATE \EJCHEMICALLY 2 ETCHEDTO PROWDE A GROOVED PATTERN r v Alli-II GROUND CLEARANCE. Houas AREDR\LLED 6 III I FOP ELECTRICAL THROUGH-CONNECTIONS D\F LECTR\C MATF.R\AL \S BONDED \NTO GROOVES AND GROUND CLEARANCE HOLES COPPER LAYERSARE. DEPOEATED OVER BOTH SURFACES COPPER \S SELECTWELY ETCHED TO LEAVETHE. DESHPED CJRCUU' PATTERN A coNDucTwE BoNDme MATEmAL l5 A DEPOSITEDONTO METAL GROUND AREAS A FH N\ OF DELECTRlG ADHESIVL MATER\AL \sDEPOSLTED oven THE D|ELECTRIC INTHE COVER PLATE; PLATES ARE THENLAMWATED THROUGH COHNECTlON": ARE PROWDED BY DRHJJNG AND PLAHNe, COPPER\m'o HOLES COPPER \5 SELECHVELY ETCHED FROM THE. DiELECT'RlC. $URFACE5TO ELECTR\CALL \SOLATE THROUGH- CONNECWONS FROM THE GROUND PLANESuvvavrops BQ/AN E. 5154/? RA YMO/VD A. STEPHENS R0854 c. WILLIAMS March23, 1971 a SEAR ET AL Re. 27,089

r PLANAR coAx'mL ICIRCUITRY Original Filed Feb. 4. 1965 I s Sheets-Sheet:s

//vvA/To/?5 BP/A/v E. SEAR RA vmo/va A. STEPHENS ROBERT C. WILLIAMSUnited States Patent 27,089 PLANAR COAXIAL CIRCUITRY Brian E. Sear,Woodland Hills, Calif., Raymond A.

Stephens, Dallas, Tex., and Robert C. Williams, Woodland Hills, Calif.,assignors to The Bunker-Ramo Corporation, Stamford, Conn.

Original No. 3,351,816, dated Nov. 7, 1967, Ser. No. 430,321, Feb. 4,1965. Application for reissue Oct. 24, 1969, Ser. No. 869,978

Int. Cl. H01b 11/06; Hk 1/14 US. Cl. 317-101 15 Claims Matter enclosedin heavy brackets appears in the original patent but forms no part ofthis reissue specification; matter printed in italics indicates theadditions made by reissue.

ABSTRACT OF THE DISCLOSURE A structure for supporting andinterconnecting electrical circuit components. The structure iscomprised of a stack of electrically conductive plates.Interconnections, effectively constituting coaxial transmission lines,are formed using the conductive plates as ground planes. Alignedrecesses are formed in opposed surfaces of the plates. Dielectricmaterial is disposed in the recesses with a conductive path being formedbetween the-dielectric material filled recesses. Adjacent plates arebonded together by an electrically conductive bonding material.

This invention relates to the manufacture of electrical components and,more particularly, to a circuit panel having circuit conductors providedtherein and extending to one or both surfaces thereof, and to themanufacture of such a circuit panel so as to define within the same aplurality of coaxial conductors electromagnetically isolated from oneanother yet having enhanced heat absorbing characteristics fordissipating the heat produced by active components conditionally held byor positioned within the circuit panel itself.

In recent years there has been an increasing emphasis onmicrominiaturization of electronic equipment and circuits. In the pastfew decades, notably since the concept of ceramic substrate printedcircuits was first suggested in the 1940s for a radio proximity fuseassembly for the United States Army, substantial changes have takenplace in the techniques of electronic circuit construction. Even priorto this Army work, the inventor Ducas, US. Patent No. 1,563,731, grantedDec. 11, 1925, described the production of circuit connections betweenvarious pieces of electrical apparatus by printing or otherwisedepositing a film pattern of conductive material onto an inorganicdielectric substrate.

Today, the early ceramic printed circuit and the Ducas printed circuit,in simplified and in complex networks, are complemented by printedwiring assemblies in many permutations and variations. There are nowwell over different commercial methods of producing printed or etchedcircuits, nearly all of which are based on the use of laminated plasticsor ceramic materials as the insulating and supporting member. Typically,the laminated printed circuits are manufactured through a process inwhich a circuit pattern or network is delineated by using a photo resiston the face of a preformed insulating sheet having a metal surfacebonded thereto. The portion of the metal surface which is not covered bythe photo resist pattern is subsequently etched away to yield thedesired conductive pattern on the insulating board surface.

These etched foil and other similar techniques are described by thepioneer Baynes in US. Patent No. 378,423, Feb. 28, 1888, and by D. K.Rider in Metals Progress, 74 (3); 81-85 (1958). When a ceramic substrateis desired, the conducting circuit pattern may be printed by employingtechniques such as evaporation, sputtering. electro-deposition,screening, and so forth. Etching of a surface metal film can also bedesirably employed, as in the manufacture of metal plated plasticboards.

While the aforementioned printed circuit techniques are improvementsover the earlier method of providing insulated metal wire as a linearpoint-to-point connection between various circuit elements, therequirements of extremely high speed computer logic circuits and theirminiaturization requires a new level of sophistication in terms ofprecision and tolerances which have not been susceptible of practicedrealization The state of microminiaturization has been achieved wherenow there is as much to be gained from the development of improved andeconomic means for interconnecting electrical circuit components as fromthe employment of very small discrete components and electronicmicro-circuits and functional blocks. In a present day aerospacecomputer, for example, interconnections represent 70% of the computersystems total volume utilizing state-of-the art printed circuittechniques discussed hereinafter.

Prior to the present invention one technique for shielding circuitryinvolved the use of multiple plates. The circuitry itself is then madeon a central isolating circuit board having opposite first and secondetched conductive surfaces. This board is then sandwiched between twoother boards each comprising an insulating sheet with a conductiveground plane deposited at the outer layers. This technique brings abouta measure of shielding of the circuit leads left by etching of thecentral board. Obviously, however, the shielding is incomplete and highsignal level carrying leads have, according to this prior art technique,to be sufi'iciently spaced so as to reduce cross-talk to some acceptablelevel. According to the present invention, high level signal carryingleads are completely surrounded by a grounded structure. Moreparticularly the present invention permits the realization of a novelcircuit configuration having this characteristic but that cannonetheless be manufactured by automated techniques and does not requiremanual operation on individual elements. With the techniques of theinvention, it is desirable to maintain certain minimum distances betweenthe signal carrying leads and the ground structure, which depends uponthe frequency and impedance requirements of the circuit. This of coursewill impose certain limits on the degree to which the circuitry may beminiaturized. However the degree of miniaturization possible with thetechnology according to the invention is not dictated by the necessityof avoiding cross-talk but solely by the single ended characteristics ofeach circuit taken separately. Consequently, the technique according tothe present invention opens entirely new roads for the layout ofcircuitry, especially significant in systems having high pulserepetition rates with the attendant increased significance of thedimensional features of the circuit layout.

In accordance with the present invention there is provided a compact,efficient and inexpensive planar coaxial circuit interconnection meansuseful in interconnecting electronic circuits and components. Suchinterconnection means, in. further accord with the present invention, isfabricated by techniques which lend themselves to the economicalproduction of high precision circuitry on a commercial scale. In apreferred form of the invention, the conductive circuit paths which inpart form the coaxial circuit interconnection means are defined withinbut electrically isolated from a self-supporting planar body, formed ofa material which is characterized by high heat and electricalconductivity.

A feature of this invention is a rigid multi-board structure havingaccurately defined mating mirror-matched :hannels to receive dielectricmaterial and a circuit pat- ;ern. This multiple cooperating boardstructure enables very precise spacing of the circuit relative to itsmetal ground planes and also enables the utilization of highly 'efinedphotographic techniques and metal removal steps which further makepossible the mass production of such zoards to high electricaltolerances.

As will be seen from the following description, the planar circuitinterconnection means provided by the nstant invention is particularlyuseful in satisfying the :lectrical requirements of the latesthigh-speed computer :ircuitry and microwave equipment, and is furthercharacterized by a high efiiciency in design, use of materials, andmanufacture, to provide for the realization of improved technicalperformance, increased reliability, reiluced costs, and ease ofproduction.

It is therefore an object of the present invention to providefabrication techniques for preparing multiiayered, high reliability,planar interconnection circuitry :haracterized by cross-talk and noiseelimination in high speed circuitry, with signal transmission up to andat kilomegacycle computing rates.

It is still another object of the invention to provide a novel circuitstructure characterized by compact interconnection planes makingpossible further miniaturiza- :ion of computer equipment and reducingthe complexity 3f interconnecting a large number of function system:lements.

Another object of the present invention is to provide for high speedinterconnections having welldefined transmission impedances reducedelectromagnetic interference problems between stages, as well as providea structure having excellent heat dissipationproperties and capable ofself-support.

Other objects and advantages of the present invention will become morereadily apparent from the following detailed description of the novelfabrication techniques and unique structure provided within the presentinvention, particularly when taken in conjunction with the appendeddrawings, in which:

FIG. 1 illustrates the multi-layered coaxial circuit, with a. portioncut away to reveal the circuit pattern disposed within the multi-layeredcircuit assembly.

FIG. 2 is a section of a three-layered planar coaxial :ircuit composite.

FIG. 3 sets forth the major steps in preparing the planar :oaxialcircuitry.

FIG. 4 diagrammatically sets forth an embodiment showing the structuralrelationship between the mother board, the dielectric material, theconducting pattern disposed therewith, and a second mating boardphysically :onstructed so as to intimately receive the mother board andits circuit pattern.

FIG. 5 illustrates the manner in which a number of integrated circuits,thin film circuits, or other microcircuit functional elements, or activeand passive components, may be interconnected and mounted within themetal circuit board byemploying the invention.

FIG. 6 is a complete functional circuit assembly with microcircuitelements containing a number of active and passive elements mountedwithin the multi-layered planar coaxial circuit body with appropriatelyshielded interconuecting paths lying completely within the metallicbody.

FIG. 7 shows a multi-layered stack of planar coaxial circuits, similarto FIG. 6 including microelectronic functional elements, and suitablysealed with a cover there over.

FIG. 8 depicts a number of planar coaxial circuits in stackedrelationship with other like circuits disposed perpendicular thereto andelectrically interconnected by pins within the shielded assemblies toprovide a compact, interlocked eggcrate like lattice structure.

In the practice of the present invention to minimize cross-talk, thedesired circuit pattern to be defined within the planar coaxial circuitcomponent of FIG. 1 is first selected, wherein the metal plate 1,suitably aluminum, copper, magnesium, low alloy steel, or other sheetingabout 0.05 in thickness and suitably thicker for mounting componentstherewithin, is provided with the desired cir cuit pattern. The groovedpatterns are preferably provided through the removal of metal, by meansphotochemically or electro-chemically etching to the desired size (about30 mils deep and 80 mils wide) based on the desired electricalparameters of the final circuit. These grooves are then filled with adielectric material 5. External connectors 3 and connector strip 22 areprovided to make connection to the carefully positioned circuit pattern6 and to other parts of the electrical apparatus, The multiple boardsmay be joined in the usual fashion such as by providing fastenersthrough the registration holes 4, and preferably are laminated togetherunder heat and pressure to provide a permanent multi-board unitarystructure.

The section view of the multi-layer circuit element shown in FIG. 2reveals the interior design thereof. The metal base plate 1b and itscover plate 1c are provided with openings or grooves filled with a lowdielectric constant material 5, which provides electrical isolationbetween the precisely located conducting circuit layer 6 relative to itsground planes 1b and 1c. Also shown in FIG. 2 is a through-connection 7which is prepared by drilling through the dielectric material 5 followedby metal plating, suitably copper, various solders, silver, etc. of thewalls of the hole to provide for a plated-through hole joining circuitsdisposed on both sides of the board. Before joining the boards togethera conductive bonding agent 11 and a dielectric adhesive 5a are screenedonto the mating surfaces as shown. To promote accuracy of alignment andgreater circuit precision, areas 12 are provided to intimately cooperatewith the raised recessed copper plated areas 14. Step areas 14 alsoprovide adjacent circuit shielding.

In FIG. 3, there is diagrammatically set forth the manufacturing stepsinvolved in preparing one of the circuits of the instant invention. FIG.3(a) shows an aluminum base plate 1b having a grooved pattern 2 orchannel provided therewithin. The second major step involves drillingground clearance holes 8 for electrical through-connections as shown inFIG. 3(b), followed by introduction of a low dielectric constantmaterial 5 into the grooves and ground clearance holes followed byheating or otherwise curing the polymeric material and causing thedielectric material to be bonded to the aluminum board. Any excessdielectric material is then removed as by lightly sanding the exposedsurface of the plate so that the surface of the dielectric is coplanarwith the board. In FIG. 3(d) is shown the step of depositing a copperlayer 10 about 1 mil thick over both surfaces of the aluminum plate,followed by FIG. 3(e) chemical etching to selectively remove the copperfrom one side of the aluminum plate excepting that portion which is thedesired layered conductive circuit pattern 6 which is very preciselypositioned over the center portions of dielectric 5. The next step shownby FIG. 3(f) involves further copper plating of the conductor pattern toabout 2 mils thickness and then providing a conductive bonding compound11, which may be conveniently a lead-tin or any other low melting alloysolder or an epoxy loaded with metal particles, which is deposited ontothe metal ground areas prior to laminating. Shown in FIG. 3(g) is thecover plate 1c having been etched to leave a mating dielectricprotruding beyond the cover board surface or preferably a dielectricadhesive 5a from the aluminum ground planes 1b and 1c. Any number ofmultiples of the preceding nine basic steps can be used in theproduction of circuits wherein a number of aluminum boards are providedin a stacked relationship.

FIG. 4 shows one of the preferred embodiments wherein portions 12 of thealuminum cover plate 1c have been removed, preferably by chemicaletching between and around the epoxy-filled grooves so as to promote anintimate mating between the base board 11) and the cover board 1c byaccepting layers 11 (a conductive bonding agent) and 14 (electroplatedcopper) therein. It has been found particularly advantageous to etchaway all of the aluminum cover plate mating surface although theperipheral land areas might well remain unetched and base plate 1bunplated in the opposed cooperating surface portions.

FIG. shows a self-supporting metal body 1, suitably cast or mechanicallyformed to provide the desired grooved circuit pattern 2 disposed withinthe metal body. The body also has ground clearance holes 8 appropriatelydrilled for electrical through-connections, and has the metal removed inselected portions thereof so as to provide cavities 21 coated with avery thin layer of heat conducting dielectric material for the mountingof functional electronic blocks or electrical components such astransistors, diodes, capacitors, magnetic or optical information storageelements, and so forth, within the body portions. Tunnels 22 may beprovided for transporting fluid cooling means, such as oil, through thestructure and preferentially around high heat build-up areas. They maybe provided vertically or may be located at the mating surface for easeof preparation. Alternatively, the functional electronic elements 15 maybe inverted and placed onto a prepared circuit pattern disposed over thethin dielectric layer 5b so that intimate electrical contact is made atthe time of insertion into the cavity. Thus the element 15 electricalcontacts are turned toward and physically contact a circuit pattern 6therebelow without further wiring steps. Connections to the mountedcomponents or functional electronic blocks are provided by theelectrical through-connections 7 to the major circuit portions disposedthereinbelow.

FIG. 6 illustrates a complete electronic assembly incorporating a numberof discrete monolithic, or other micro-electronic functional blocks 15,and interconnecting circuitry 6 mounted thereon and therewithin beingcompletely shielded from adjacent portions or stages by the mother-board1, in close heat conducting relation thereto and electrically isolatedby insulating material 5b and provided with external electrical leads 3and pin leading to a power supply and other equipment. Othermodifications are, of course, possible including the providing of alarge number of such multiple stacks. Utilization of the instantinvention makes possible the employment of relatively large areastructures due to the dimensional stability and self-supportingmother-board characteristics thereof.

FIG. 7 shows a planar coaxial circuit stack, comparable to that shown inFIG. 6, but also provided with metal covering means 17 to provide forhermetic or other forms of sealing. In lieu of a metallic cover 17 theencapsulation means may desirably be a silicaceous or vitreous ceramicmaterial overlying the microcircuit elements 15 and other circuitportions 6 detailed in FIG. 6.

FIG. 8 illustrates another method of assembling the electricalcomponents of the instant invention to accomplish high packing densitieswhile yet retaining the other desirable features of the invention.Electrical terminals are provided for external connection thereto andthe mnlti-layered coaxial planar circuit is shown attached to asupporting structure 18 and is physically interconnected by boardportion 19 joined to the underlying stack or suitably through fasteners.Electrical interconnections between the multiple boards in interlockedrelationship are provided by pins 20 plugged into variousplated-through- 6 hole receptacles making suitable electricalconnections to the desired shielded circuit patterns within each stackrespectively. Other physical arrangements, such as cordwood modulearrays, decked assemblies, and so forth, can also be used.

The basic process and a preferred embodiment for the roduction of ourplanar coaxial circuitry suitably involves the employment of an aluminumsheet, 1100 series, /2 hard, about 0.093" thickness, as the startingmaterial. In sequence, we proceed:

(1) Prepare an Al blank (base plate) by shearing to the wanted size;drill registration or tooling holes and mate to another blank of thesame dimensions; one blank being for the base with the other being forcovering circuitless portion. Provide a single master art plate.

(2) Prepare for or photo resist mask or screen application by drysanding of blank surfaces, cold solvent degreasing, and Iriditetreatment followed by oven drying. (Iridite is a proprietary name for asurface treating solution, used on aluminum, made by Allied ResearchProducts Corporation, Baltimore, Md.)

(3) Dip or spray KMER (Kodak Metal Etch Resist, manufactured by EastmanKodak, Rochester, N.Y.) or similar product, airless solution (4 partsresist and 5 parts thinner) at about 35 p.s.i. to blank and allow toovendry until tacky. Expose and develop photo resist followed bytouch-up and post baking at 150 F. for 30 minutes.

(4) Chemically etch in 20 percent NaOH solution for about 2 /2 hours toa depth of approximately 32. mils and to a channel width ofapproximately mils While simultaneously deoxidizing every 30 minutes andreversing blank each cycle. Subject the board to thorough cold rinsing.

(5) Provide interconnecting holes in blank by drilling to artworkpattern employing bit size of about 0.80" diameter. Wet sand to removeKMER resist and follow up with zincate treatment of blank or treatmentwith a similar mild surface etching solution.

(6) Copper electroplating in cyanide bath of all aluminum surfaces,including channels, to an approximate 1 ml. depth. Utilize bus baragitation; mask registration holes; and plate with current density ofabout 20 amps/ ft.

(7) Fill completely the troughs or channel patterns with a lowdielectric constant (desirably about 2) material such as ScotchcastXR-5090, made by Minnesota Mining and Manufacturing Company, or anunmodified nonpolar polymer (polyolefins, polystyrenes, andpolytetrafluoroethylene) or with a more polar polymer such as an epoxyor phenolic; pull a vacuum to insure that the channels are withoutvoids; followed by curing at a temperature of about F.

(8) Lightly sand or otherwise remove excess epoxy so that its exposedsurface is substantially coplanar With the surface of the board.

(9) Electroplate copper on all aluminum surfaces to about 1 milthickness (after masking of registration holes and zincate treatmentutilizing current densities of 20 amps/ft. with bus bar agitation ofbath. Clean surfaces and follow with electroless copper deposition ontodielectric surfaces employing desirably the iShipley No. 328 mixture(made by The Shipley Company of Wellesley, Maine), with subsequent acidcopper sulphate plating to about 1.5 mil depth.

(10) Apply photo resist, KPR (Kodak Photo Resist, manufactured byEastman Kodak, Rochester, N.Y.), or equivalent product to base plate;print using com osite negative/ positive while exposing conductor linesand metal surfaces surrounding epoxied area.

(11) Drill conductor line pads (30 mil diameter); etch unexposedaluminum areas surrounding circuit pattern; and strip KPR resist usingchemical stripers or wet fine grinding.

(12) Electroplate copper (about 2 mils) over entire aluminum surface tobuild a raised or step configu- -ation completely surrounding thedielectric-filled groove attern and the transmission lines platedthereon. The plating is done in an acid bath employing violent airagitation and current densities up to 40 amps/ftF.

(13) Screen onto the surfaces of the step or raised areas a conductiveadhesive material, preferably a silver loaded epoxy.

(14) Prepare cover plates by following manufacturing steps No. 17recited above to provide for opposed cooperating board(s) about .062"thick having dielectric material bonded within the grooved pattern. Usethe same master art plate for mirror-image.

(15) Etch mating surface of the aluminum cover board to a 4 mil depthutilizing 20 percent NaOI-I solution to provide a board having asaw-tooth or step configuration with the projections being thedielectric material bonded within the board grooves.

(16) Screen onto the dielectric raised portions a film of an insulatingadhesive (Minnesota Mining and Manufacturing Companys XR-9050) The finalproduction step involves taking the prepared base plate (having acircuit on one or both sides) and the prepared cover plate (or number ofcover plates for a many-layered structure) and joining them into aunitary composite as shown in FIG. 2. Preferably the joining stepinvolves inserting the registration pins into the plates followed bylaminating in a platen press at about 50 p.s.i. pressure, a temperatureof about 150 F., and curing for about 2 hours.

Various attempts have been made by workers to reduce or eliminatecross-talk in high speed logic circuits. One recent approach has been toprovide a strip transmission line in a sandwich configuration comprisingdual center conductors in close contact, plus two or more layers ofsolid dielectric sheets separating the conductors from dual groundplanes. The dielectric sheets maintain a spacing between the centerconductors and the ground planes. However the relationship is unprecisedue to dimensional instability of the dielectric sheet material ascompared to the instant invention which employs a rigid self-supportingmetal board with far superior physical stability.

Coupling between closely spaced transmission lines decays exponentiallywith dielectric spacing, hence high packing densities can be employedwith the instant planar configuration. Power handling capabilities ofthe instant cricuitry are much greater than heretofore due to the highheat dissipation inherent in the self-supporting metal boards, withmegawatt peak powers being possible-and limited essentially only tocorona or physical breakdown of the conductive pattern per se. Theimpedance of the transmission lines in our invention can be selected andaccurately defined within a wide range of values by simply correlatingdielectric conductor geometry with ground plane spacing.

In high-speed computer circuits it is useful to provide one or two logiclevels per nanosecond, for example, and about 15-25 nanoseconds permemory read-regenerate cycle. A number of problems immediately arisewhen concerned with these speeds, including packaging densities, wiringdelay (l /z interconnection-corresponds roughly to a delay of one logiclevel), as well as cross-talk between adjacent transmission lines andtheir connectors, etc. High packaging densities always raise the furtherproblems of heat dissipation which is essential to the properfunctioning of electronic equipment.

For high power electrical circuits the planar coaxial structure can bereadily provided with dynamic heat removing means such as fiuids flowingthrough tunnels in the boards 1b and 1c; Higher power handling limitsfor the circuitry can be realized by substituting a low-dielectricconstant fluid for the solid dielectric 5 disposed within the coverplate 1c, and providing for coolant circulation by external means. Thisfeature enables actual immersion of the transmission lines 6 into thecoolant. Additional static cooling means can be provided through finsdisposed over the non-mating surfaces of the cover plate 1c, and ascastmetal foam or honeycomb plates can also be suitably employed.

We have satisfactorily solved for the first time these problems ofsignal transmission at kilomegacycle computing rates. The simplicityinherent in our invention also invites economic savings. This inventionmay well provide impetus for a further extension of the high speedcomputer state-of-the-art.

The invention as hereinabove described, and set forth in the appendeddrawings, is obviously capable of various modifications withoutdeparting from the inventive concept contained herein, and manyapparently widely different embodiments of the same can be made withinthe spirit and scope of the claims without departing therefrom, and itis intended that all such matters contained in the accompanyingspecification shall be interpreted as illustrative only and certainlynot in any limiting sense.

What is claimed is:

1. An electrical circuit comprising:

a first self-supporting electrically conducting board, said board formedwith a recess in a first surface thereof;

a first mass of dielectric material disposed in the recess of said firstboard and bonded thereto;

a layered conductive circuit pattern contiguous with and overlying saidmass of dielectric material;

a second electrically conductive board having a recess formed in a firstsurface thereof, said first and second boards being stacked with saidfirst surfaces in contact with each other and with said recesses inopposed alignment to form a cavity; and

a second mass of dielectric material disposed Within the recess of thesecond board and bonded thereto, so that said circuit pattern is spacedfrom said first and second conductive boards but substantially e11-closed in the cavity formed therewithin.

2. An electronic circuit comprising:

a first relatively flat conductive body having a recess formed on thelarger surface thereof;

a second conductive body having a recess formed on the larger surfacethereof;

said first and second conductive bodies joined together and conjointlydefining a cavity substantially enclosed by conductive material;

the recess in said first body filled with a first solid dielectriclayer; and

circuit means including a layered conductor overlying said first soliddielectric layer;

the recess in said second conductive body containing a second soliddielectric layer that is disposed juxaposite said circuit means, so thatsaid circuit means are surrounded by dielectric material and spaced inrigid spaced relationship from said first and second conductive bodies.

3. The electronic circuit of claim '2 including at least one elementcavity formed in a surface of one of said bodies;

a thin layer of dielectric material disposed in said element cavity; and

one or more electronic elements disposed in said element cavityelectrically insulated from said bodies by said thin layer of dielectricmaterial and electrically connected to said circuit means.

4. An electrical circuit as in claim 3 comprising:

encapsulation means overlying said electronic elements.

5. An electrical circuit as in claim 4 wherein said electronic elementscomprise integrated monolithic and multichip circuits.

6. In electrical apparatus, the combination comprising:

a first electrically conductive plate having a trough in each of theupper and lower surfaces thereof, the upper trough passing over atleasta portion of the lower trough spaced therefrom at a predeterminedposition therealong, said first plate having a hole therethrough at saidpredetermined position;

second and third electrically conductive plates fixed to opposite sidesof said first plate, said second and third plates having troughs at thesame positions as the troughs in the surfaces of said first plateadjacent thereto;

dielectric fixed in said troughs;

a first conductive strip fixed in said dielectric between said first andsecond plates;

a second conductive strip fixed in said dielectric between said firstand third plates; and

a conductor extending through said hole connecting said strips.

7. An electrical circuit structure including:

first and second electrically interconnected conductive plates supportedin superposed relationship with first surfaces of said plates adjacentone another;

aligned and opposed recesses formed in said first surfaces of said firstand second plates;

dielectric material disposed between said recesses; and

an electrical conductor supported by said dielectric material betweensaid recesses and electrically insulated from said conductive plates.

8. The circuit structure of claim 7 including electrically conductivematerial bonding together said first surfaces of said first and secondplates.

9'. The circuit structure of claim 7 wherein said recesses formed insaid first surfaces of said first and second plates are completelyfilled with said dielectric material.

10. An electrical circuit structure comprising a stack of planar membersincluding first and second self-supporting planar members, each of saidfirst and second planar members being conductive and having a pluralityof openings therein following respective predetermined paths, dielectricmaterial disposed in said openings, and an electrical conductorsupported by vthe dielectric material in each opening so as to beelectrically isolated from its respective conductive planar member, eachconductor following a path corresponding to the path followed by itsrespective opening, said stack of planar members also includingself-supporting planar members provided adjacent said first and secondplanar members and having conductive portions arranged and electricallyconnected thereto so as to provide complete electrical shielding foreach conductor.

11. The invention in accordance with claim 10, wherein 1O electricalinterconnection means are included within said stack for providing aninsulated electrical path passing from a predetermined conductor of saidfirst planar member to a predetermined conductor of said second planarmember.

12. The invention in accordance with claim 11, wherein said electricalinterconnection means includes a shielded and insulated conductivematerial path between said predetermined conductors and perpendicular tosaid planar members.

13. The invention in accordance with claim 11, wherein said stack ofplanar members includes a third planar member containing electricalcomponents, and wherein said electrical interconnection means alsoprovide insulated electrical paths within said stack betweenpredetermined ones of said components and predetermined ones of saidconductors.

14. The invention in accordance with claim 13, wherein said third planarmember and predetermined other planar members of said stack providecomplete electrical shielding for said components as well as for eachconductor.

15. The invention in accordance with claim 14, wherein said componentsare provided in the form of an electrical package having electricaloutputs, wherein said third planar member is provided with insulatedelectrical contacts to which the electrical outputs from said packageare electrically connected, and wherein said electrical connection meansis provided within said stack as a plurality of insulated conductivematerial paths perpendicular to the planar members of the stack, andwherein predetermined ones of said planar members also provide completeelectrical shielding for said insulated conductive material paths.

References Cited The following references, cited by the Examiner, are ofrecord in the patented file of this patent or the original patent.

UNITED STATES PATENTS 3,234,320 2/ 1966 Wong.

DARRELL L. CLAY, Primary Examiner,

US. Cl. X.R.

